Abstract
The power consumption, especially the leakage power, is a big issue in nanometric
technologies. In scaled technologies, the impact of lowering the supply voltage in order to ensure the low
leakage power, leads to a decrease in robustness. The paper investigates the effect of lowering the supply
voltage on the robustness of a 6T SRAM cell, both in saturation and sub-threshold regimes. The Static
Noise Margin (SNM) is evaluated analytically and compared with HSPICE simulations for 130nm, 90nm
and 65nm Berkeley Predictive Technology Models (BPTM) [9]. Our results show that the SNM of the
cell decreases nonlinearly with a linear decrease in the supply voltage. The proposed analytical model is
also used to predict the minimum value of the supply voltage that preserves the data stored in a 6TSRAM
cell, which is found to be approximatively 5% of the nominal value.
