Optimizing the IDEA Algorithm for FPGA using Vitis HLS
- Authors
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Alexandru Constantin Bala
National University of Science and Technology Politehnica Bucharest
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Gheorghe Decebal Popescu
National University of Science and Technology Politehnica Bucharest
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- Abstract
- This article presents an optimized hardware implementation of the International Data Encryption Algorithm (IDEA) for FPGAs using High-Level Synthesis (HLS). To avoid expensive modulo operations, the design employs a custom, division-free modular multiplier over the Fermat prime 65537. Leveraging C++ arbitrary precision types, the architecture explores the trade-off between temporal pipelining and spatial unrolling to maximize data throughput. Hardware correctness is validated through C/RTL co-simulation against a software Golden Model. Finally, a hardware loopback test with an inverted key schedule successfully restores the original plaintext, confirming full system functionality
- References
- Cover Image
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- Published
- 2026-09-29
- Issue
- Vol. 28 No. 3 (2026)
- Section
- Articles
- License
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Copyright (c) 2026 Journal of Control Engineering and Applied Informatics
This work is licensed under a Creative Commons Attribution 4.0 International License.
